The present invention relates generally to delta-sigma modulator based fractional-N phase locked loop frequency synthesizers and deals more particularly with a digital delta-sigma modulator for controlling a multi-modulus frequency divider in the feedback path of the phase locked loop.
Digital frequency synthesizers have long been used in communication systems, particularly RF communication systems, to generate RF signals carried over RF channels. In frequency synthesis, it is desirable to achieve the selected frequency output in as little time as possible with any spurious output frequencies minimized. It is known to create a frequency synthesizer by placing a frequency divider function between the voltage-controlled oscillator (VCO) output and the phase frequency detector (PFD) in a phase-locked loop (PLL), wherein the VCO output frequency is an integer-N multiple of the input reference frequency to the PFD. The spurious outputs in question are usually associated with phase detectors and occur at the phase detector operating frequency, which is generally the same as the channel spacing. Incorporating a fractional-N division function in the PLL provides a number of advantages and helps overcome problems of spurious frequency outputs by allowing the phase detector to operate at a much higher frequency for the same channel spacing.
A number of methods are known that are based upon the concept of integer-N frequency synthesis to realize the fractional-N division function and include pulse swallowing, phase interpolation, Wheatly random jittering and delta-sigma modulation to control the multi-modulus, including dual-modulus, frequency dividers to provide the division function. Of the known methods, a delta-sigma modulator realization of a fractional-N frequency synthesizer is desirable and preferable to achieve low phase noise, fast settling time, fine channel resolution and wide tuning bandwidth. The delta-sigma modulator fractional-N frequency synthesizer is based on the concept of division ratio averaging, wherein an integer frequency divider rather than a fractional frequency divider is used. The division ratio is dynamically switched between two or more values, effectively providing a non-integer number division function. One of the most important advantages of using the delta-sigma modulator to control a multi-modulus divider is the ability to shape phase noise introduced by the delta-sigma modulator controlled fractional-N division function. A problem generally associated with such a delta-sigma modulator fractional-N frequency synthesizers is the appearance or presence of fractional spurious levels at a fractional offset frequency. The fractional spurious levels may also appear at the fractional offset frequency harmonics. The fractional spurious levels in delta-sigma modulator based fractional-N frequency synthesizers may originate from several sources including the operation of the delta-sigma modulator itself, coupling between the multi-modulus prescaler or charge pump driving the loop filter and the outside world through power supply feeds or substrates, and the nonlinearity of the charge pump. The fractional spurious frequencies may also originate from the spacing error or timing error of the multi-modulus prescaler.
It would be desirable therefore to provide a delta-sigma modulator in a fractional-N frequency synthesizer that achieves low phase noise, fast settling time, fine channel resolution and wide tuning bandwidth.
It is an object therefore of the present invention to provide a digital delta-sigma modulator in a phase locked loop fractional-N frequency synthesizer that provides an increased multi-modulus input control range.
It is another object of the present invention to provide a digital delta-sigma modulator in a phase locked loop fractional-N frequency synthesizer wherein the desired fraction multi-modulus control input signal is generated in the interval between xe2x88x921 and +1.
It is a further object of the present invention to provide a digital delta-sigma modulator in a phase locked loop fractional-N frequency synthesizer wherein the desired frequency is achieved by adding a fractional frequency to an integer frequency less than the desired frequency or subtracting a fractional frequency from an integer frequency greater than the desired frequency.
It is a still further object of the present invention to provide a digital delta-sigma modulator having a direct input for a modulation data signal in a two""s complement format.
It is a yet further object of the present invention to provide a digital delta-sigma modulator wherein the modulation data signal is processed in the modulator for use as a direct modulation fractional-N frequency synthesizer.
One advantage of the delta-sigma modulator embodying the present invention, as further described hereinbelow, is a modulation data signal, a dithering signal or a sum of different signals can be directly connected to the input of the modulator.
A further advantage of the delta-sigma modulator of the present invention is a desired or a selected channel frequency can be achieved by adding or subtracting a fractional component part to or from an integer component part of the desired frequency wherein the fractional component part can be set at any value between xe2x88x921 and +1.
Another advantage of the delta-sigma modulator of the present invention is the modulation data signal or dithering signal can be directly connected to the input in a two""s complement format.
A still further advantage of the delta-sigma modulator of the present invention is the dithering signal can be a sinewave in two""s complement format.
A yet further advantage of the delta-sigma modulator of the present invention is the input signal in two""s complement format can be the sum of all or any combination of the modulation data signal or dithering signal including the fractional component part.
In accordance with a first aspect of the invention, a digital delta-sigma modulator for controlling a multi-modulus divider in a fractional-N frequency synthesizer includes a plurality of delta-sigma modulator stages cascaded in a feed-forward circuit topology and the number of stages define an Nth order delta-sigma modulator. The modulator has a direct connection input means for receiving a N-bit input control word defining a desired frequency for selection. The desired frequency is broken down to have an integer component part and a fractional component part. The modulator also has sign-bit input means for receiving a direction signal indicating the desired frequency selected by adding the fractional component part to the integer part or by subtracting the fractional component part from the integer part. Logic means coupled to the delta-sigma modulator stages are provided for detecting and determining the amount and direction of a frequency from the desired frequency to produce a weighted M-bit output multi-modulus divider control word.
Preferably, the feed forward cascaded circuit topology comprises a cascaded sequence of delayed accumulators.
Preferably, the feed forward cascaded circuit topology comprises a pipelined accumulator topology wherein the input control word is pipe shifted and the output control word is align shifted.
Preferably, the logic means further comprises timing compensation registers in the carry overflow signal output of the accumulator and differentiation circuit means for performing a differential calculation on the carry overflow signal output.
Preferably, the differentiation circuit means comprise a cascaded sequence of differentiators.
Preferably, the N-bit input control word is in a two""s complement format.
Preferably, the N-bit input control word is dithered to produce an average zero dither N-bit input control word.
Preferably, the N-bit control word is dithered as a sine wave signal in a two""s complement format.
In accordance with another aspect of the invention, a delta-sigma modulator for controlling a multi-modulus divider in a fractional-N frequency synthesizer includes a plurality of cascaded feed forward accumulators wherein the number of accumulators is the order of the delta-sigma modulator. Although described as a third order delta-sigma modulator, the design considerations and implementation apply to higher orders as well. The first accumulator includes a first input for receiving an N-bit modulation data signal representative of a desired channel frequency selection and a second input for receiving a SIGN-bit control word representative of the direction for adding or subtracting a frequency offset to a fixed frequency to generate the frequency corresponding to the desired selected channel frequency. The first accumulator includes a feed forward output coupled to the input of a first next following accumulator, a first carry signal C1 output indicative of an overflow or underflow condition, and a SIGN bit signal output indicative of the direction of the overflow. The first carry signal C1 and the SIGN bit signal are logically combined in logic means and a first logic output control word is generated. The first next following accumulator includes a feed forward output coupled to the input of a second next following accumulator, and a second carry signal C2 output indicative of an overflow or underflow condition. The second next following accumulator includes a feed forward output coupled to a feedback input, and a third carry signal C3 output indicative of an overflow or underflow condition. The carry output signals C2 and C3 from the first next following and second next following accumulators, respectively are summed such that the carry output signals add to a net summation equal to zero so as to not affect the fractional control word input. The resultant carry output signal C2 and C3 summation is added to the first logic output control word to provide a multi-modulus division function control word.
Preferably, the N-bit modulation data signal is in a two""s complement format.
In a further aspect of the invention, each of the feed forward outputs are coupled through a respective delay register, and the first carry signal C1 and the SIGN bit signal output are coupled through a first and second plurality of delay registers, respectively. The second carry signal C2 is coupled through a third plurality of delay registers and the third carry signal C3 is coupled through a fourth plurality of delay registers.